The invention relates generally to stacked microelectronic modules. Specifically, the invention relates to a device comprised of stacked integrated circuit (IC) package layers, such as ball grid array packages (BGA) or flip chip bonded IC chip layers that are interconnected to an external circuit by means of an interposer layer and an interface printed circuit board (PCB).
In the microelectronics industry, there are significant advantages to stacking and interconnecting commercial off the shelf (COTS) integrated circuit packages. The primary advantage of stacking layers is maximum utilization of limited surface area on a printed circuit board. Vertically stacking integrated circuit packages provides increased circuit density without requiring additional printed circuit board space. Further, stacking integrated circuit packages reduces signal lead lengths between the stacked components, reducing parasitic inductance and capacitance, which in turn, allows the circuits to operate at very high clock speeds. The use of COTS components also provides the advantage of ensuring the stack contains fully burned in, tested and functional die, i.e., ensures the use of known good die (KGD) in the stack.
Industry has recognized the value of stacking COTS integrated circuits as is reflected in U.S. Pat. No. 6,026,352 to Eide, U.S. Pat. No. 6,806,559 to Gann, and U.S. Pat. No. 6,706,971, to Albert, all to common assignee, Irvine Sensors Corp. and each of which is incorporated fully herein by reference.
The current microelectronic packaging trend is toward ball grid array packages which comprise an array of solder ball interconnections for I/O to and from the internal integrated circuit die on the lower surface of the BGA package. The solder balls are reflowed on a registered set of conductive pads on an external circuit for interconnection therewith. It is therefore desirable to provide a device that takes advantage of the benefits of stacking and that can accommodate ball grid array packages or other layers that comprise an array of registered I/O pads for interconnection, which device can be adapted for use on a standard BGA printed circuit board pattern.